System for providing a video display having differing video display formats

ABSTRACT

A system for providing a video character display containing at least two different types of video display formats which are comprised of independently self-generated digital-to-video scan signals. These scan signals are combined to provide a composite video signal which, when supplied to a television display device which utilizes a raster scan-line pattern, provides the various video display formats in different scan-line areas of the display screen. Each of the display formats is individually controllable. The various types of display formats which are provided include a ticker display, a text and/or graph display, and a crawl display. Means are provided for controlling the movement of the character display across the screen so as to vary the rate of movement of the character display across the screen in accordance with the rate of information input to the system. In this manner, a smooth video display format is provided at all input rates. Each display format comprises a plurality of character spaces and the system determines the character to be displayed in the given space on a space-by-space basis.

United States Patent Coombe SYSTEM FOR PROVIDING A VIDEO [75] Inventor:Thomas R. Coombe, Berlin, N.J

[73] Assignee: Reuters Limited, London, England [22] Filed: May 21, 1971[21] Appl. No.: 145,858

[521 US. Cl. 340/154, 340/324 AD 1 [58] Field of Search 340/324 A, 154

[56] References Cited UNITED STATES PATENTS 3,462,739 8/1969 Scantlin340/154 3,566,090 2/1971 Johnson 340/154 X 3,623,070 11/1971 Johnson etal..... 340/154 X 3,651,511 3/1972 Andrews et al.... 340/154 X 3,676,8507/1972 Goldman et a1. 340/154 3,500,327 3/1970 Belch er et al 340/154 I3,559,207 1/1971 Atkinson 340/324 A 3,643,252 2/1972 Roberts 340/324 A3,611,348 10/1971 Rogers.... 340/324 A 3,624,632 11/1971 Ophir 340/324 A[4 1 Apr. 2, '1974 Primary Examiner-David L. Trafton Attorney, Agent, orFirm-Lawrence G. Kurland [57] ABSTRACT A system for providing a videocharacter display containing at least two different types of videodisplay formats which are comprised of independently selfgenerateddigital-to-video scan signals. These scan signals are combined toprovide a composite video signal which, when supplied to a televisiondisplay device which utilizes a raster scan-line pattern, provides thevarious video display formats in different scan-line areas of thedisplay screen. Each of the display formats is individuallycontrollable. The various types of display formats which are providedinclude a ticker display, a text and/or graph display, and a crawldisplay. Means are provided for controlling the movement of thecharacter display across the screen so as to vary the rate of movementof the character display across the screen in accordance with the rateof informatron input to the system. In this manner, a smooth videodisplay format is provided at all input rates. Each display formatcomprises a plurality of character spaces and the system determines thecharacter to be displayed in the given space on a space-by-space basis.

21 Claims, 13 Drawing Figures 3| CHARACTERS TICKER DISPLAY "STOCKS 15MIN. DELA 3| CHARACTERS TEXTAND/OR GRAPH 8 Rows v 32 CHARACTERS TExTAND/OR GRAPH 3| CHARACTERS C-RAwL PATENTEDAPR 2 I974 SHEET 1 UP 8ATIORNEYS- I PATENTEDAPR 21974 3.801.961

SHEET 8 UF 8 I FIG. 8A. v FIG. 8B.

TEXT

FIG. 80.

[3|CHARACTERS TICKER DISPLAY IFS/900 |3| CHARACTERS TICKER D|SPLAYJ\/902"STOCKS I5 MIN. DELAY" [\vgozl 3| CHARACTERS TEXTAND/OR GRAPH] [32CHARACTERSTEXTAND/OR GRAPH I L 3| CHARACTE S CRAWL f J INVENTOR I.THOMAS R. COO B BY i KLM Q MM @W! ATTORNEYS.

SYSTEM FOR PROVIDING A VIDEO DISPLAY HAVING DIFFERING VIDEO DISPLAYFORMATS BACKGROUND OF INVENTION 1. Field of the Invention The presentinvention relates to systems capable of providing a video displaycontaining at least two different types of video display formats.

Description of the Prior Art There are several prior art video displaysystems. Prior art systems, however, are normally of the type whichutilize a television camera in order to provide the information to bedisplayed on the screen. In such a system, at least one televisioncamera is provided for each display area on the screen to whichdifferent information is to be supplied. Furthermore, in such systems,the television cameras are slaved to each other and the various displayareas on the screen are, therefore, not independently controllable withrespect to each other. These systems are not capable of displayingdifferent types of display formats on the video display screen so thatif it is desired to display two types of information whicheach lendthemselves to a different type of display format, such as a display of anews report for a predetermined interval of time, and a display of stockticker information in a continuously moving format, these prior artsystems cannot accomplish this. In an attempt to overcome this problem,prior art systems have utilized a separate television camera forscanning a moving tape containing the stock ticker inthe type in whicha'selected one of a plurality of digi- I tallyistored messages may bedisplayed either as a message page or in a moving format across thevideo display screen. In such prior art systems, a combination of agiven sequence of dot signals and a given sequence of line signals isutilized to define a character space area. Such systems are disclosed in[1.8. Pat. Nos. 3,426,344; 3,422,420 and 3,345,458. These prior artsystems, however, are not capable 'of providing different types ofdisplay formats on the commonvideo display screen; rather, only one typeof display format is displayed. Thus, as was previously mentioned, whenit is desired to display two different types of display formats thesesystems cannot be utilized. In addition, such prior art systems whichutilize a moving character display across the video display screen arenot able to compensate for variations in the input rate of data to thesystem when such variations occur. Thus, if the device feedinginformation data to the system is such as a keyboard, as the rate ofinput of information by the keyboard operator varies, the movingcharacter display on the screen will appear discontinuous or jerky-sothat a smooth display will not be provided as the data input ratevaries. 'Thus, the display provided is undesirable as it is annoying tothe viewer. Furthermore, such prior art video display systems capable ofconverting stored digital signals into a video display do not havesufficient flexibility in order to display alphanumeric information andfractions as well as graphic information simultaneously on the videodisplay screen, such as for providing a video display of a graph havingnotations thereon. Thus, although television display systems capable ofconverting binary input signals into video signals for displaying thedata in readable form on a conventional television picture tube havebeen available, they have not been utilized to maximum efficiency inareas where it is desired to display different types of informationsimultaneously, such as when it is desired to provide an up to databusiness forecast.

These disadvantages of the prior art are overcome by the presentinvention.

SUMMARY OF THE INVENTION A system for providing a video characterdisplay containing at least two different types of video display formatsis provided. These video display formats are independentlyself-generated digital-to-video scan signals which are provided indifferent areas of the television display screen. The display formatdisplayed in each of the display areas is individually controllable.Conventional scanning techniques are utilized for display of thedigital-information in readable form on a conventional televisionpicture tube. Preferably, at least one of the display formats provides amovable character dis play across the video display screen. Means areprovided for controlling the motion of this character display across thescreen by varying the rate of movement of the character display acrossthe screen-in accordance with the rate of information input to thesystem. In this manner, compensation for variations in input rate isprovided so that a smooth moving display format is provided for allinput rates. The'system is capable of providing a character displaycomposed of alphanumeric characters, fraction characters, and graphcharacters, so that a composite display of a graph having notationalinformation thereon may be provided. Each display row is divided into anumber of character spaces, a character space being defined by apredetermined sequence of linesand a predetermined sequence of dots. g I

The system determines the information to be displayedv in each characterspace on a space by-space basis so that one space may contain analphanumeric character, another space in the row may contain a fractioncharacter, and another space in the row may contain a graph character sothat the composite graph display may be provided. In addition, thesystem is capable of providing a ticker type of display, which isnormally a moving display format, a text type of display comprising aplurality of rows wherein the rows are painted on a rowby-row basis toform a message page which is held for a predetermined time, as'well as acrawl type of display which is a moving display. In this mannerdifferent types of video display formats may be simultaneously displayedon the video display screen. If desired, any one or more of theplurality of display formats may be independently removed from thecomposite video display without altering the display of any of the otherportions.

' The system is also capable of controlling the display of one or moretelevision display devices and may be utilized in conjunction with aremote computer which could be utilized to distribute differentinformation through a plurality of television monitors on a time sharedbasis. In such instance, a particular channel is assigned to eachtelevision monitor and when the channel address associated therewith istransmitted from the V computer and decoded by'the system, theparticular channel will be accessed. In such instance, if desired, thetext message page which has been painted on a given television monitorcan be held until the channel associated with this monitor is addressedagain by the remote computer.

BRIEF DESCRIPTION OF DRAWING FIG. 1 is a functional block diagram of thepreferred embodiment of the system of the present invention;

FIG. 2 is a block diagram, partially in schematic of the ticker inputbuffer portion of the system of FIG. 1;

FIG. 3 is a block diagram partially in schematic of the ticker charactergeneration portion of the system of FIG. 1;

FIG. 4 is a block diagram, partially in schematic of the text inputbuffer portion of the system of FIG. 1;

FIG. 5 is a block diagram, partially in schematic of the text memoryportion of the system of FIG. 1;

FIG. 6 is a block diagram, partially in schematic of the text displayportion of the system of FIG. 1;

Referring now to the drawings in detail, and especially to FIG. 1thereof which is a functional block diagram of the preferred embodimentof the system, generally referred to by the reference numeral 10, of thepresent invention. For purposes of clarity, the portion of the systemwhich generates the timing signals utilized for controlling operationthroughout the system, as will described in greater detail hereinafter,has been omitted from FIG. 1, although the appropriate timing signalsare shown throughout the figures. The timing signal generation networkwill bedescribed in greater detail with reference to FIG. 7 hereinafter.The system 10 of the present invention preferably includes a text inputbuffer portion 12, a text memory portion 14, a display portion 16, aticker number 1 input buffer portion 18, a ticker character generationportion 20, a ticker number 2 input buffer portion 22, a scroll inputbuffer portion 24, a scroll character generation portion 26 and 21stocks min. delay message generation portion 28. For purposes ofillustration, and not by way of limitation, the system 10 of the presentinvention will be described with respect to provision of a compositeplural display having a text and/or graph portion, two ticker portions,a delay message portion and a scroll portion. Any other desirablecombination of plural display may be accomplished without departing fromthe spirit and scope of the present invention as will become apparent toone of ordinary skill in the art from the following description.

The text input buffer portion 12, which is preferably capable ofreceiving either a text line input 30 and/or an auxiliary line input 32,such as from an external digital system, includes an input gatingcircuit comprising AND gate 34 associated with the text line input 30and AND gate 36 associated with the auxiliary line input 32, both ofwhich are fed to an OR gate 38. The output of the OR gate 38 isconnected in parallel to a conventional resynchronizer 40 and an inputregister 42. As will be described in greater detail hereinafter, theresynchronizer 40 is connected to the clock terminal of the inputregister 42. The input register 42 is connected to a character detector44 which, as will be described in greater detail hereinafter, detectsthe presence of the start bit of the input signal. The output of theinput register 42 is also connected to a storage register 46 which is inturn connected in parallel to a function decoder network 48, to bedescribed in greater detail hereinafter, which provides controlfunctions for the system 10 of the present invention, and to an addressdecoder network 50 for detecting the appropriate channel to be addressedwith the input information. The character detector 44 is also connectedin parallel to the transfer terminal of the storage register 46 forcontrolling the transfer of data from the input register 42 to-thestorage register 46, as will be described in greater detail hereinafter,and to the text memory portion 14.

The output of the storage register 46 is connected in parallel to memorynetworks 52 and 54, one such memory network being provided for eachchannel,- only two channels A and B being shown for purposes ofillustration. Each of the memories 52 and 54 is preferably a seven by256 bit memory; that is, seven stages, one per bit, each having acapacity of 256 bits. The address-decoder 50 is connected in parallel tothe load terminal of memories 52 and 54. The output of memories 52 and54 are connected in parallel to the recirculation regis ter network 56which, as will be described in greater detail hereinafter, enables thescanning of one character row of data, which is preferably 16 horizontallines.

The output of the recirculation registers 56 of the text memory portion14 is connected to a conventional character generator 58 contained inthe display portion 16. The output of the character generator 58 isconnected to a conventional output register 60 whose output is in turnconnected to an output gating network which preferably includes a pairof AND gates 62 and 64 connected in parallel, one AND gate beingprovided for each channel, AND gates 62 and 64 being connected to anenable text signal generator 66. The output of AND gate 62 is connectedto a three input OR gate 68. The other two inputs to OR gate 68 areprovided from a pair of AND gates 70 .and 72, AND gate 70 beingassociated with the ticker character generation portion 20 output andAND gate 72 being associated with the scroll character generationportion 26 output, as will be described in greater detail hereinafter.The output of OR gate 68 is connected to a conventional video mixer 74which is also connected to a sync signal generator 76 in order toprovide a composite video signal which may be transmitted to aconventional television display 78 in order to provide a plural displayof the text, ticker and scroll information, as will be described ingreater detail hereinafter. Similarly, AND gate 64 associated withchannel B, has its output connected to another three input OR gate 80whose other two inputs are provided by a pair of AND gates 82 and 84,AND gate 82 being associated with the scroll character generationportion 26 and AND gate 84 being associated with the ticker charactergeneration portion 20. The output of OR gate 80 is similarly connectedto another conventional video mixer 86 which also has a sync signalgenerator 88 connected thereto in order to provide a composite videosignal on channel B to a separate conventional television display device90, as will be described in greater detail hereinafter.

Now, generally describing the ticker number 1 input buffer portion 18,the functional diagram except for the associated timing signals andinput information signals, being preferably identical with that of theticker number 2 input buffer portion 22 and the scroll input bufferportion 24, the same reference numerals therefore being utilized forfunctionally identical components followed by the letters a and b,respectively, for input buffer portions 22 and 24. The ticker number 1input 7 buffer portion 18 preferably includes a resynchronizer Y 92connected to the ticker number 1 input 94.'The input 94 further beingconnected in parallel to an input register 96. The output of theresynchronizer 92 is connected to the clock terminal of the inputregister 96 in the same manner as described with reference to a similarconnection in the text inputbuffer portion 12. The output of the inputregister 96 is connected to a character detector 98 which senses thestart bit of the input signal, and to a storage register 100. The outputof the character detector is connected to a space detector 102 which, aswill be described in greater detail hereinafter, has its outputconnected to a motion control network 104 so as to enable movement ofthe ticker character display across the video display screen of thedisplay devices 78 and 90 in a smooth manner. The character detectorcircuit 98 via the space detector network 102 is connected to thetransfer terminal of the storage register 100 to enable the loading ofdata, the output of the storage register 100 being connected to thespace detector 102. The output of the motion control network 104 isconnected in parallel to the ticker number 1 input buffer memory 106,which is preferably a six by 32 bit memory which is'enabled by an enableticker number 1 output signal 108, and to the ticker charactergeneration portion 20.

The ticker character generation portion 20 includes a charactergeneration 110 whose output is connected to an output register 112 whichoutput, in turn, is connected to position gating circuitry 114, to bedescribed in greater detail hereinafter, the position gating network 114being responsible for the movement of the ticker character displayacross the screen. The motion control 104 is connected to the positiongating network 114 via an OR gate 1 16 which is provided with anotherinput from the motion control 1040 of the ticker number 2 input bufferportion 22. The output of the position gating network 1 14 of the tickercharacter generation portion 20 is connected to AND gates 70 and 84 ofthe display portion 16. The character generator 110 of the tickercharacter generation portion 20 is connected in parallel to the outputof the memories 106 and 106a of the ticker number 1 input buffer portion18 and the ticker number 2 input buffer portion 22, respectively.Inaddition, the output of the stocks min. delay message generator 28 isalso connected in parallel with the memory 106 and 106a outputs to thecharacter generator 1 10 of the ticker character generation portion 20.

The functional description of the scroll input buffer portion 24, as waspreviously mentioned, is identical with that previously described withreference to the ticker number 1 input buffer portion 18, except that inplace of the enable ticker number 1 output signal generator 108 there isan enable scroll signal generator 118, the balance of the functiondiagram being identical except that in place of the ticker number 1input 94 there is a scroll input and, in the ticker number 2 inputbuffer portion 22, in place of the ticker number 1 input 94 there is aticker number 2 input 121. Simi-' larly, the functional portions of thescroll character generator portion 26 are identical with that previouslydescribed with reference to the ticker character generation portion 20,the scroll character generation portion 26 including a charactergenerator 122 whose output is connected to an output register 124 whoseoutput is, in turn, connected to position gating network 126. The motioncontrol network 1041: of the scroll input buffer portion 24 has itsoutput connected also to the position gating network 126. In addition,the output of the memory 106b of the scroll input buffer portion 24 isconnected to the input of the character generator 122 of the scrollcharacter generation portion 126. The output of the position gatingnetwork 126 of the scroll character generation portion 26 is connectedin parallel to AND gates 72 and 82 of display portio TICKER NUMBER 1INPUT BUFFER PORTION Referring now to FIG. 2 and describing the tickernumber 1 input buffer portion 18 in greater detail. As was previouslymentioned, the ticker number 2 input buffer portion 22 and the scrollinput buffer portion 24 are preferably identical in structureandoperation, the only differences being in the nature of the input signalprocessed through the corresponding input buffer portion and theassociated timing signals necessary to process this input signal.However, as will be explained in greater detail hereinafter, the tickercharacter generation portion 20 and the scroll character generationportion 26 provide different types of output signals through the displayportion 16, the ticker signal, whether it be from the ticker number 1input buffer portion 18 or the ticker number 2 input buffer portion 22ultimately providing a display of associated ticker information which ispreferably sixteen lines high, the first eight lines being for displayof the letter relating to the stock symbol, the bottom eight lines beingfor the display of alphanumeric characters associated with the symbol,and the bottom ten of these lines being for display of fractioncharacters associated with this symbol. The scroll character generationportion 26 ultimately provides a scroll display which is preferably onlyeight lines high. However, for purposes of explanation, since thecircuitry associated with the input buffer portions 18, 22 and 24 areessentially the same, by way of example, only the associated circuitryof the ticker number 1 input buffer portion 18 will be described ingreater detail hereinafter;

The ticker number input buffer portion 18, as will be explained ingreater detail hereinafter, receives the ticker number 1 input 94 fromany conventional source of such information, such as a remote computer,teletype, or keyboard, the ticker number 1 input preferably being aconventional ticker code which is a nine unit code comprising a startbit, six information bits and two stop marks, this code being similar toa teletype code. This ticker number 1 input 94 is normally at EIA compatible voltage levels and is, therefore, preferably fed through aconventional level changer 130 which changes the EIA compatible voltagelevel input to TTL compatible levels in a conventional manner. Theoutput of this level changer 130 is connected in parallel toresynchronizer 92 and to the data input of input register 96 which ispreferably an eight bit input register. As waspreviously mentioned, theoutput of the resynchronizer 92 is connected to the clock terminal ofthe input register 96. The resynchronizer 92 also preferably receives aclock input via path 132, the clock input preferably being sixteen timesthe frequency of the ticker input 94. The resynchronizer 92, which ispreferably a conventional resynchronizer which functions in aconventional manner, resynchronizing on the leading edge of each newspace pulse to insure center sampling of the input pulses'and tominimize spurious noise pulses, may be any conventional type, such asone comprising a flip-flop arrangement connected in a conventionalfashion to a divide-by-16 counter, whichcounter receives the clock input132 such as through an inverter.

The eight bit input register 96 is preferably connected to the storageregister 100 to provide a parallel transfer thereto. Preferably, one ofthe stages of the eight bit input register 96 is also connected inparallel to the conventional character detector circuit 98 which, aswill be explained in greater detail hereinafter, senses the start bit.This character detector 98 may be any conventional character detectorcircuit such as one comprising a flip-flop network. As will be explainedin greater detail hereinafter, the character detector 98 receives timingsignals VB3 via path 134 and SDET via path 136 from the basic timingchain to be described in greater detail with reference to FIG. 7, andfrom the space detector. 102 associated with the input buffer portion18, respectively. The character detector 98 is connected to theclear-reset terminal of the input register 96 via path 138 so as toprovide a reset pulse thereto. In addition, the character detector isconnected to the load terminal of the storage register 100 via path 140.The space detector 102 is preferably a conventional type of spacedetector network comprising a flip-flop 142, and receives timing inputsignals VB2 and C6 from the basic timing chain (FIG. 7). The data inputterminal of the flip-flop 142 is preferably connected to the output ofan OR gate 144 which has one input connected in a feedback path to theoutput of the flip-flop 142 and the other input connected to the motioncontrol network 104 to be described in greater detail hereinafter.

The output of the storage register 100, which conventional storageregister 100 preferably comprises six four-bit-recirculation memories,one for each output bit, is connected to memory 106 so as to preferablysupply a parallel transfer of data thereto. Memory 106 also preferablycomprises six thirty-two-bitrecirculation memories. As will be explainedin greater detail hereinafter, memory 106 preferably is connected to themotion control network 104 so as to receive transfer pulses labeled XFERand XFER via paths 146 and 148. The output of memory 106, is preferablyalso a parallel transfer of data, each of the six parallel transfer bitsbeing connected as an input to an associated two input NAND gate 150,152, 154, 156, 158 and 160. These NAND gates through inclusivepreferably have the other input thereto connected in parallel to aconventional enable ticker number 1 generator 108 (FIG. 7) to receive anenabling pulse therefrom via path 866 in order to provide a paralleltransfer of ticker bits TKBI, TKB2, TKB3, TKB4, TKBS and TKB6 via paths162, 164, 166, 168, and 172 respectively, to the ticker charactergeneration portion 20 which will be described in greater detailhereinafter.

Now describing the motion control network 104 of the ticker number 1input buffer portion 18, the motion control network 104 providing acharacter incrementing function, as will be described in greater detailhereinafter in the discussion of the operation of the input bufferportion 18. As will be described in greater detail hereinafter, themotion control network 104 cooperates with the position gating network114 of the ticker character generation portion 20 to control themovement or motion of the resultant ticker display across the videodisplay screen. The resultant motion is dependent on the rate of loadingthe data into the storage register 100; that is, whether 1, 2, 3 or 4bits of data are loaded into the storage register 100 for a givenassociated bit, before the associated recirculating memory is able totransfer the data from the storage register to the memory 106. Themotion control network 104 preferably includes a motion control register174, which is preferably a conventional four bit register, and an outputmotion control counter 176, which is preferably a conventionaldivide-by-IZ counter, and associated gating circuitry so as to providethe appropriate control signals to the position gating network 114 inorder to control the motion of the ticker display. The C6 timing pulseprovided from the basic timing chain shown in FIG. 7 is fed via path 178through an inverter 180 to one input of a NAND gate 182 whose otherinput is the transfer pulse XFER which is also fed via path 148 to thememory 106. The output of the NAND gate 182 is connected in parallel toa pair of NAND gates 184 and 186 which also have their other inputsconnected in parallel to a clock input CK provided via path 188 from aconventional clock generator as shown in FIG. 7.

The output of NAND gate 186 is connected to the clock terminal of themotion control register 174. The data input terminal of the motioncontrol register 174 is connected to the output of'a two input NOR gate190, one input of which is the transfer pulse XFER which is alsoprovided via path 146 to the memory 106. The output of the motioncontrol register 174 preferably comprises four parallel bits Q0, Q1, Q2,Q3 and, in addition, the complement of Q3 which is O3, provided viapaths 192, 194,196, 198 and 200, respectively. The O3 output bit viapath 198 is connected in parallel to one input of a two input OR gate202, the outer input of gate 202 being a timing signal LC (loadcharacter) via path 204. The output of OR gate 202 is provided inparallel as one input to OR gate 144 of space detector 102 via path 206,and as an input to NOR gate 190 via path 208. The output of OR gate 202via path 208 is also provided in parallel to the preset input of aflipflop 210 whose output in the set state is 81 via path 212. Theinputs to the flip-flop 210, as will be described in greater detailhereinafter, are provided from the output motion control counter 176.

The O bit via path 192 from motion'control register 174 is provided asan input to an AND gate 214 whose output is connected to one input of atwo input NOR gate 216. The O1 output bit of motion control register 174via path 194 is provided as an input to another AND gate 218 whoseoutput is connected to the other input of the NOR gate 216. The outputof NOR gate 260 is connected to the data input terminal of-a flipflop220 which provides an output S4 via path 222 in the 6 state. The outputin the 6 state is also provided via a feedback path 224 as an input toAND gate 218. The O state output of flip-flop 220 is connected via path226 to the clock input of a flip-flop 228.

The input to the data terminal of the flip-flop 228 is connected to theoutput of a two input NOR gate 230, one input to NOR gate 230 beingconnected to the output of an AND gate 232, the other input to the NORgate 230 being connected to the output of AND gate 234. The O1 outputbit of motion control register 174 bia path 194 is provided as an inputto AND gate 232 and the Q2 output bit of motion controlregister 174 viapath 196 is provided as an input to AND gate 234. The O state output offlip-flop 228 is a pulse S3 via path 236. The 6 state output is'alsoconnected via a feedback path 238 to an input to AND gate 234. The Qstate output of flip-flop 228 is connected via a path 240 to the .clockterminal input of another flip-flop 242 whose 6 state output is apulse'S2 via path 244. The data input terminal of flip-flop 242 isconnected to the output of atwo input OR gate 246. One input to OR gate246 is the Q2 output bit from the motion control register 174 via path196, while the other input to OR gate 246 is connected to the outputof atwo input NOR gate 248. One input to NOR gate 248'is the 0 3 output bitof motion control register 174 provided via path 200 while the otherinput to NOR gate 248 is connected to the 0 state output of flip-flop242 via path 250. The signal 6 provided from the basic timing chain ofFIG. 7, to be described in greater detail hereinafter, is connected inparallel as an input to flip-flops 220, 228 and 242 via path 178.

Now describing the gating circuitry associated with the output motioncontrol counter 176. Another timing signal G2 provided from the basictiming chain'shown in'FIG. 7 via path 254 is connectedthrough aninverter 256 to one input of a two input NOR gate 258. The other inputto NOR gate 258 is the 81 output of flipflop 210 via path 212. Theoutput of NOR gate 258 is connected through one input of a two input ANDgate 260 whose output is connected to one input of a four input NOR gate262. The other input to AND gate 260 is connected to the C1 timingsignal output via path 264 of the basic timing chain shown in FIG. 7.This signal is connected in parallel to one input of another AND gate266, the output of AND gate 266 being connected to a different input toNOR gate 262. The other input to AND gate 266 is connected to the S3output of flip-flop 228 via path 236. A third input to NOR gate 262 isconnected to the output of another two input AND gate 268 whose inputsare a timing signal C 2 provided from the basic timing chain shown inFIG. 7 via path 270, and the S2 output of flip-flop 242 piovided viapath 244. The fourth input of NOR'gate 262 is connected to the output ofanother AND gate 272 whose input is connected to the S4 output offlip-flop 220 via path 222. The output of NOR gate 262 is connected toone input of a two input NOR gate 274 whose other 10 input is a timingsignal delay clock (1T1?) supplied from the output of a conventionaltiming generator 852 shown in FIG. 7 via path 276. The output of NORgate 274 is connected to an input to-the output motion control counter176.

The outputs of the output motion control counter 176 are parallelsignals D1, D2, D3 and D4 provided via paths 278, 280, 282 and 284,respectively. As will be explained in greater detail hereinafter, the D1output via path 278 represents the output of the most rapid moving stageof counter 176 and the D4 output of counter 176 via path 284 representsthe slowest moving stage of the counter 176. The D1 output via path 278is connected in parallel to one input of an NAND gate 286 and toassociated circuitry, such as flip-flop 210, via path 288. The D2 outputvia path 280 is connected as one input to another NAND gate 290. The D3output via path 282 is connected in parallel to one input to anotherNAND gate 292 and to one input of another NAND gate 294 via path 296.The D4 output via path 284 is connected in parallel to one'input of atwo input NAND gate 298 and to the other input of NAND gate 294 via path300. The other inputs of NAND gates 286, 290, 292 and 298 are connectedinparallel to the output of an NOR gate 302 whose inputs, for purposesof ticker display, are timing signal W amdR2 which are provided from thebasic timing chain of FIG. 7 via paths 304 and 306 to, provide an enablesignal to gates 286, 290, 292 and 298. Theoutputs of gates 286, 290, 292and 298 are the complemeents I71, 52, D3 and D4 of the respective inputsD1, D2, D3 and D4 provided 7 via paths 291, 293, 295' and 297,respectively. When the network shown in FIG. 2 is utilized as a scrollinput buffer, terminals 304 and 306 are grounded as shown by the dottedlines. 1

The D4 output via path 284 is also connected through an inverter 308 toa flip-flop 310. The Q state output terminal of flip-flop 310 isconnected to the data input terminal of another flip-flop 312'whichreceives the timing signal C6 from the basic timing chain of FIG. 7 asanother input thereto. The 6 state output terminal, of flip-flop 312 isconnected in parallel to the data terminal and clock terminal offlip-flop 310 to provide the transfer output pulse XFER viapath 148. The0 state output terminal of flip-flop 312 provides thetransfer pulse XFERvia path 146. The timing signal 63 1 provided from the basic timingchain of FIG. 7 via path 264 is connected in parallel through aninverter 314 to provide timing output signal C1 via path 316, and to theclear input terminal of flip-flop 312.

The motion control circuitry 104 is also connected to the storageregister to provide a transfer pulse thereto. The transfer pulse XFERprovided via path 146 is connected to onevinput of a two input OR gate320 whose output is connected via path 322 to the transfer input ofstorage register 100. The other input to OR gate 320 is the enable loaddata (ELD) output signal from character detector 98 via path 140. Thissignal via path is fed through an inverter 324 to the input of OR gate320 and also provides the signal LC (load character) via path 204 to ORgate 202. The ELD signal via path 140 is also connected in parallel toone input of a two input NOR gate 326 whose output via path 328 is alsoconnected to the transfer input of the storage register 100. The otherinput to NOR gate 326 is connected to the output of another two inputNOR gate 330. One input to NOR gate 330 is connected to timing signalTKE (ticker enable) via path 332, which signal is preferably groundedwhen this input buffer network is utilized as a scroll input buffer, asshown by the dotted lines. The signal TKE (ticker enable) via path 332is also connected in parallel to an inverter 334 whose output is thecomplement thereof m via path 336. The other input to NOR gate 330 isconnected to the output of an NAND gate 338 whose two inputs are two ofthe seven parallel bits provided as the output of input register 96,preferably the sixth and seventh bits.

TICKER CHARACTER GENERATION PORTION Now referring to FIG. 3 anddescribing the ticker character generation portion 20 in greater detail.As was previously mentioned, the circuitry associated with the tickercharacter generation portion 20 is preferably identical with thatassociated with the scroll character generation portion 26 with theexception of the type of signal input and the various timing signalsutilized to control the processing of the signal through the charactergeneration circuitry. In addition, the character generator 122 utilizedfor scroll character generation preferably differs from the charactergenerator 1 utilized for ticker character generation in that thescroll'character generator 122 is preferably not programmed to providefraction characters, although, if desired, this could also beaccomplished. As will be explained in a more detailed description of theoperation of the system of the present invention, and as was previouslymentioned, the timing signals associated with the scroll charactergeneration portion 26 as compared to those associated with the tickercharacter generation portion are such as to provide only eighthorizontal scan lines for a scroll character space as opposed to sixteenhorizontal scan lines for a ticker character space. Since, however, theticker character generation portion 20 and the scroll charactergeneration portion 26 are preferably identical but for the exceptionsmentioned above, only the ticker character generation portion will bedescribed in greater detail hereinafter.

The character generator portion 110 of the ticker character generationportion 20 is preferably a conventional character generator such as aread only memory (ROM) preprogrammed for a desired character generationfunction. Preferably, the character generator 110 is capable ofgenerating both alphanumeric characters and fractions in response to theticker bit outputs of memory 106 via paths 162, 164, 166, 168, 170 and172 in the horizontal line scan signals. If desired, the conventionalcharacter generator could be a single metaloxide semiconductor (MOS)read only memory chip preprogrammed for these functions, a pair of MOSread only memory chips wherein one is preprogrammed for alphanumericcharacters and the other for fraction characters, or a single read onlymemory' (MOS) chip which is preoprogrammed for alphanumeric charactersin conjunction with supplementary TTL logic in order to generate thenecessary fractions which are outside the range of the preprogrammed.MOS chip. The horizontal line scan timing signals which are utilized tointerrogate the read only memory character generator 110 in conjunctionwith the ticker bit input signal via paths 162 through 172 are providedfrom the basic timing chain of FIG. 7 in a manner to be described ingreater detail hereinafter. Suffice it to say at this point that inresponse to these interrogation sigand nals the character generatorprovides an appropriate output character via a parallel transfer intothe conventional output register 112 which is preferably a two stageregister.

The output register is connected to a master oscillator associated withthe basic timing chain of FIG. 7 via path 340 so that the register 112will shift at the video dot frequency provided by the oscillator, aswill be described in greater detail hereinafter. The output register 112is also provided with a transfer pulse XFERTK via path 342 from anOUTPUT REGISTER-OUTPUT TRANSFER PORTION 344, which will be described ingreater detail hereinafter.-Transfer pulse XFERTK permits the parallelloading of the output register 112 from the character generator 110. Theoutput of the output register 1 12 is transferred in parallel to theposition gating network 114. Oscillator timing pulse OSC via path 340 isalso passed through an inverter 344 to provide a timing pulse OSCT whichis the complement thereof via path 346. One of the parallel output bitsfrom output register 1 12 is connected via path 348 to one input of atwo input NAND gate 350, the other input to gate 350 being an enabledelay output signal (EDO) provided via path 352 from a conventionaltiming generator 354 shown in FIG. 7, and omitted from this figure forpurposes of clarity. As will be described in greater detail hereinafter,the output of gate 350 is a timing signal delay output (DO) via path 356which signal enables a black on white display of the message (STOCK 15MIN. DELAY) on the video display screen instead of the normal white onblack display which is prefera-' bly provided for the tickerinfonnation.

Another parallel bit output of output register 112 is provided via path358 to one input of a two input AND gate 360 whose output is provided asone input to a NOR gate 362. The other input to NOR gate 362 isconnected to the output of another two input AND gate 364 which has oneinput connected to another one of the parallel bit outputs of outputregister 112 via path 366. The other input to AND gate 364 is connectedin parallel to one input of another two input AND gate 368 whose otherinput is connected to another one of the parallel bit outputs of outputregister 112 via path 370. The output of AND gate 368 is connected toone input of a two input NOR gate 372 whose other input is connected tothe output of another AND gate 374. One input of AND gate 374 isconnected to another parallel bit output of output register 112 via path376 and the other input to gate 374 is connected in parallel to oneinput of AND gate 360.

Another one of the parallel bit outputs of output register 112 isconnected to one input of another two input NAND gate 378 via path 380,the other input to NAND gate 378 being connected in parallel to oneinput of another two input NAND gate 382. The other input to NAND gate382 is connected to another parallel bit output of output register 1 12via path 384. The parallel connected inputs of AND gates 364 and 368 areconnected in parallel via path 386 to the output of an inverter 388whose input is connected to the D2 output associated with theoutputmotion control counter 176 via path 293. The parallel connectedinputs of AND gates 360 and 374 are connected in parallel via path 390to the output ofan inverter 392 whose input is the D3 output associatedwith output motion control counter 176 via path 295. The outputs ofinverters 388 and 392 are also connected in parallel to the inputs of atwo input NOR gate 394 whose Output is connected in parallel to oneinput of NAND gates 378 and 382 via path 396. The output of NOR gate 372and the output of NAND gate 382 are respectively connected to the inputof a two input OR gate 398 whose output is connected to the input of atwo input AND gate 400. The other input to AND gate 400 is connected tothe m output associated with motion control counter 176 via path 297,this D 4 output being connected in parallel to the input of an inverter402.

The output of inverter 402 is connected to one input of a two input ANDgate 404, the other input to AND gate 404 being connected to the outputof a two input OR gate 406. The two inputs of OR gate 406 are connectedto the outputs of NOR gate 362 and NAND gate 378, respectively. Theoutputs of AND gates 400 and 404 are connected to the inputs of a twoinput NOR gate 408 whose output is connected in parallel to the datainput terminal of a pair of flip-flops 410 and 412, respectively. Theclock terminal of flip-flop 410 is connected to the oscillator timingsignal OSC via path 340, and the clock terminal of flip-flop 412 isconnected to the OSCT timing signal output of inverter 344 via path 346.The 6 state output of flip-flop 410 is connected to one input of a twoinput AND gate 414 and the 6 state output of flip-flop 412 is connectedto one input of another two input AND gate 416.

The D l output associated with output motion control counter 176 viapath 291 and the enable delay output signal (EDO) via path 352 of timinggenerator 354 (FIG. 7) are connected to the inputs of, a two input NORgate 418 whose output is a timing signal D1 via path 240 which isconnected in parallel to one input of a two input NOR gate 422. Theother input to NOR gate 422 is connected in parallel to the EDO input toNOR gate 418, the output of NOR gate 422 being a timing signal m" viapath 424. Timing signal D1via path, 420 is provided as the other inputto AND gate 416 and timing signal D71 via path 424 is provided as theother input to AND gate 414. The output of AND gates 416 and 414 areconnected to the inputs of a two input NOR gate 426 whose output isconnected to one 428 is connected to one input of the two input NANDgate 430 which provide a ticker position gating output signal TICKER tothe display portion 16 via path 432. The other inputto NAND gate 430 isconnected to a portion of the position gating network referred to as theposition gating-horizontal blanking portion or window generation circuit434.

This horizontal blanking portion 434, as will be described in greaterdetail hereinafter, provides a window which is thirty one characterslong in order to provide a display of this length in this window. Moreparticu-. larly, the other input to NAND gate 430 is connected to the 6state output of a flip-flop 436 whose Q state output is connected to oneinput of a two input NAND gate 438, the other input to NAND gate 438being connected to the GT timing signal generated from the basic timingchain of FIG. 7 via path 264. The output of NAND gate 438 is connectedto one input of a two input OR gate 440 whose other input is connectedto the G6 output of the basic timing chain of FIG. 7 via path 178 andwhose output is connected to the data input terminal of flip-flop 436.Flip-flop 436 is connected to the output register-output transferportion 344. More particularly, flip-flop 436 is connected in parallelto the 6 state output of a flip-flop 442 associated with the outputtransfer portion 344 and to the data input terminal of flip-flop 442,the 6 state output of flipflop 442 being the transfer pulse XFERTK viapath 342. The output of an NOR gate 444 is also connected to theflip-flop 442, the input to NOR gate 444 being connected to the timingsignal output m of the basic timing chain of FIG. 7 via path 446. Theclock terminal of flip-flop 442 is connected to the timing signal outputV131 of the basic timing chain of FIG. 7 via path 448.

TEXT INPUT BUFFER PORTION For purposes of clarity, before describing thedisplay portion 16 in greater detail, the balance of the circuitryassociated with providing the signal to the display portion 16 will nowbe described. Referring now to FIG. 4 and describing the text inputbuffer portion 12 in greater detail. The text line input via path 30,which may be provided from a remotely located computer,

keyboard, or teletype type of device, or any other conventional type ofinformation input device, is connected to the input of a conventionallevel changer 450 which is capable of changing EIA compatible voltagelevels to TTL compatible voltage levels. The output of level changer 450is connected to one input of a two input 'AND gate 452 whose other inputis connected'to the enable line output signal ELINE provided via path.

454 from a function decoder 456 of the function decoder network 48. Theoutput of AND gate 452 is connected to one input of a two input OR gate458, the other input to OR gate 458 being connected to the output ofanother two input AND gate 460. One input to AND gate 460 is connectedto the enable line output signal ELINE provided via path 462 fromfunction decoder 456, and the other input to AND gate 460 is connectedto the output of another conventional level changer 464 capable ofchanging ElA compatible voltage levels to TTL compatible voltage levels.The input to level changer 464 is connected to the auxiliary line inputAUX. LINE INPUT provided via path 32.

The output of OR gate 458 is connected in parallel to conventionalresynchronizer 40 and to the data input of inputregister 42, which ispreferably an eight bit input register. The output of resynchronizer 40,as was previously mentioned, is preferably connected to the clock inputterminal of input register 42. The resynchronizer 40 is connected to theconventional clock signal generator shown in FIG. 7 via path 132, theclock signal preferably being 16 times the input rate of the text lineinput signal provided via path 30 or the auxiliary line input signalprovided via path 32. Resynchronizer 40 is connected to the G4 timingsignal provided from the basic timing chain of FIG. 7 via path 466. Theinput register 42 is connected to a conventional character detector 44and to the storage register 46 in a manner similar to that previouslydescribed with reference to the interconnection of input register 96,character detector 98 and storage register 100 of the ticker number 1input buffer portion 18. The input register 42 preferably provides aparallel output, character detector 44 preferably being connected to oneof the parallel output bits of input register 42 to sense the occurrenceof a start bit.

The character detector 44 is connected to the transfer terminal input ofstorage register 46 so as to cause a parallel transfer of the datapresent in input register 42 when the start bit is detected. Inaddition, the character detector 44 is connected to the clear-resetterminal of input register 42 via path 468 to provide a reset pulse RIRto the input register 42 after the transfer of the data from the inputregister 42 to the storage register 46. The character detector 44 isconnected to the basic timing chain of FIG. 7 to receive timing pulsesG1 and VB3 via paths 264 and 446, respectively. The character detector44 operates in a conventional manner to sense the bits transferred tothe storage register 46 to determine if the character is a displayablecharacter in which instance an enable load data signal ELD will be sentvia path 470 to address decoder 472, a displayable character beingdefined as one of the 64 ASCII characters including space plus the graphand fraction characters. If the character detected by the characterdetector 44 is not a displayable character, but rather is a controlcharacter such as line feed (LF), carriage return (CR), or start of text(STX then the control signal CONT or CONT will be provided from thecharacter detector 44 via paths 472 and 474, respectively.

Storage register 46 preferably provides a parallel output which isillustrated by parallel bits B1, B2, B3, B4, B5, B6 and B7 via paths476, 478, 480, 482, 484,486 and 488, respectively. The parallel outputprovided via paths 476 through 486 inclusive provides a parallel inputto address decoding matrices A, B and Z, 490, 492 and 494, respectively.As will be described in greater detail hereinafter, these decodingmatrices are conventional decoding matrices which provide a conventionaloutput control pulse in response to the decoding of a given selectedinput signal code. For purposes of illustration, decoding matrix 490 isassociated with channel 1 or A for video display device 78, decodingmatrix 492 is associated with channel 2 or B for video display device 90and decoding matrix 494 is as sociated with both devices 78 and 90 tosimultaneously turn them both on, as opposed to only turning on onechannel. Decoding matrices 490, 492 and 494 are connected in parallel tothe enable load data signal output ELD provided via path 470 fromcharacter detector 44 and to an enable load header signal output ELI-lprovided via path 496 from a function decoder 498 of function decodernetwork 48.

The output of decoding matrix 490 is connected to the input of aflip-flop 500 whose output is connectecd in parallel to one input of apair of two input NOR gates 502 and 504 associated with the addressdecoder network 50. The other input to NOR gate 504 is a clear pulse C1provided via path 506 from a function decoder508 of the function decodernetwork 48. Another input to NOR gate 502 is connected to the output ofathree input NAND gate 510 whose inputs are a coincidence pulse COINprovided via path 512 from the conventional coincidence circuit 514shown in FIG. 7, the enable load data pulse ELD provided via path 470and the enable load header pulse ELI-l provided via path 516 fromfunction decoder 498. The output of NOR gate 502, which is the load datasignal LDl, is connected in parallel to the load input terminal ofmemory 52 .via path 518 and to one input ofa two input OR gate 520, theother input to OR gate 520 being connected to the output of NOR gate504. The output of OR gate 520 is a clear plus C rl provided via path522 to the clear terminal of memory 52. The output of NAND gate 510 isalso connected in parallel to one input of a two input NOR gate 524.

Decoding matrix 492 has its output connected to a flip-flop 526 whoseoutput is in turn connected in parallel to the other input of NOR gate524 and to one input of another two input NOR gate 528. The other inputto NOR gate 528 is the clear pulse CI: provided via path 506. The outputof NOR gate 528 is connected to one input of an OR gate 530. The outputof NOR gate 524 is connected in parallel to the other input of OR gate530 and to the load data terminal of memory 54 to provide a load datasignal LD2 via path 532. The output of OR gate 530 is connected tothelear terminal of memory 54 to provide a clear pulse CL2 via path 534 tomemory 54. Control signals start of header (8 611) and end of text (ETX)provided via path 536 from function decoder 498 are connected inparallel to flip-flops 500 and 526. Decoding matrix 494 is connected inparallel to flip-flops 500 and 526 for simultaneously controlling theoperation of these flip-flop upon the decoding of the appropriate inputsignal.

The control signal inputs, as will be explained in greater detailhereinafter, are detected by means of the function decoder network 48comprising function decoders 456, 498, 508, 538, 540, 542 and 544. Byway of example, and not limitation, various parallel output bits fromstorage register 46 are illustrated as providing the various controlvunction inputs to the function decoder network 48. Now describingfunction decoder 498. The parallel output bits provided via paths 480,482 and 484 from storage register 46 are connected to the inputs of athree input NAND gate 546 whose output is connected to one input of atwo input NOR gate 548. The othe input to NOR gate 548 is the controlpulse output CONT from character detector 44 via path 474. The output ofNOR gate 548 is connected in parallel to one input of a pair of twoinput NAND gates 550 and 552, respectively. The other input to NAND gate550 is connected to parallel bit outputs 476 and 478 of storage register46, and the other input to NAND gate 552 is connected to parallel outputbit 476 of storage register 46. The output of NAND gate 550 is connectedin parallel to function decoder 508 to provide 'a start of text signal(T X via path 554, and to the input to a flip-flop 556 which providesthe enable load.

header signal FLT-I via path 516 in one state, and the enable loadheader signal ELH via path 496 in the other state. The output of NANDgate 552 is connected in parallel to flip-flop 500 to provide the startof header (SO H) and end of text (W) signals thereto via path 536, andto flip-flop 556.

Now describing function decoder 544. Parallel output bits 480, 482 and484 from storage register 46 are connected to the inputs of a threeinput NAND gate 558 whose output is connected to one input of a twoinput NOR gate 560. The other input to NOR gate 560 is connected to thecontrol pulse output CONT of character detector 44 via path 474. Theoutput of NOR gate 560 is connected to an input of NAND gate 562 whoseother input is connected to parallel output bits 476 and 478. The outputof NAND gate 562 is a tape control signal TAPE provided via path 564 tofunction decoder 456.

Now describing function decoder 542. An output coincidence signal COINprovided via path 512 from coincidence circuit 514 is connected inparallel to the input of an inverter 566 to provide the complementthereof, the coincidence signal COIN, and to one input of a two input ORgate 568. The other input to OR gate 568 is connected to the enable loadheader signal output ELI-I of function decoder 498 via path 516. Theoutput of OR gate 568 is connected to one input of a two input NAND gate570 whose other input is connected to the enable load data output ELD ofcharacter detector 44 via path 470. The output of NAND gate 570 isconnected to the data input terminal of a flipflop 572. The timingsignal W33 from the basic tirning chain of FIG. 7 is also connected tothe flip-flop 572 via path 446. In addition, the preset terminal offlip-flop 572 is connected to a master oscillator shown in FIG. 7 viapath 340. The output of flip-flop 572,in the state is the advancecontrol pulse A )T/ provided via path 574 to function decoders 508 and540 and, as will be described in greater detail hereinafter, to a cursorcharacter counter 576 (FIG. 7).

Now describing function decoder 508. The advance control pulse ADVprovided via path 574 from function decoder 542, and the enableload-header pulse ELI-I via path 496 from function decoder 498, areconnected to the inputs of a two input NOR gate 580 whose output isconnected to a flip-flop 582. The timing signal C6 via path 252 isprovided to flip-flop 582 from the basic timing chain of FIG. 7. Theoutput of flip-flop 582 is connected to one input of a two input OR gate584 whose output is the clear pulse CT provided via path 506. The otherinput of OR gate 584 is connected to the 0 state output of a flip-flop586. The 6 state output of flip-flop 586 is connected to the input ofanother flip-flop 588 whose output is connected to the data inputterminal of flip-flop 586. A timing signal W is provided from the basictiming chain of FIG. 7

to flip-flop 586 via path 590. Flip-flop 588 is also connected to thestart of text (S TT( output of NAND gate 550 of function decoder 498 viapath 554.

Now describing function decoder 538. Control signal CONT from characterdetector 44 via path 472 and parallel output bits '482 and 484 ofstorage register 46 are connected to the input of a three input NANDgate 592 whose output is connected in parallel to one input or NOR gates594 and 596. The other inputs to NOR gates 594 and 596 are connected toparallel output bit 480 of storage register 46. The output of NOR gate594.

is connected in parallel to one input of NAND gates 598, 600 and 602.The other inputs to NAND gate 598 are parallel output bits 476 and478..The output of NAND gate 598 is the control pulse or charactercarriage. return (TR provided via path 604 from function decoder 538.The other inputs to NAND gate 600 are also parallel output bits 476 and478, more particularly the compliments thereof. The output of NAND gate600 is the control character shift in ST provided via path 606 fromfunction decoder 538. The other input to NAND gate 602 is paralleloutput bits 476 and 478, NAND gate 602 providing the control charactershift out w via path 608 from function decoder 538. This input of NANDgate 602 is connected in parallel to one input of another NAND gate 610,this input being connected to the output of an NOR gate 612 whose inputis the parallel output bits 476 and 478, from which the input to NANDgates 602 and 610 is derived. Another input to NAND gate 610 isconnected to the output of NOR gate 596 which is also connected inparallel to one input of a three input NAND gate 614. The output of NANDgate 610 is connected to the input of an inverter 616 whose output isthe control character line feed LF provided via path 618 from functiondecoder 538. The other inputs to NAND gate 614 are parallel output bits476 and 478. The output of NAND gate 614 is the control character tab mprovided via path'620 from function decoder 538.

Now describing function decoder 540. The shift out 86 character outputof function deocder 538 via path 608 is connected in parallel to thedata input terminal of a flip-flop 622 and to the input of an inverter624 whose output is connected to another flip-flop 626. The controlsignal CONT output of character detector 44 via path 474 isconnected inparallel to flip-flop 622 and to another flip-flop 628. The 6 stateoutput of flipflop 622 is connected to the data input terminal offlipflop 626 and the O state output terminal of flip-flop vtrol signaloutput ADV of function decoder 542 via path 574. The, shift in controlcharacter 8T output of function decoder 538 via path 606 is connected inparallel to the data input terminal of flip-flop 626 and to g the inputof an inverter 634 whose output is connected to another flip-flop 636.The 6 state output of flip-flop 636 is connected to the clock terminalof flip-flop 626. The clock terminal of flip-flop 636 is connected tothe shift out control character output 86 of function decoder 538 viapath 608.

Now describing function decoder 456. Function de coder-456 isspecifically related to the control of a video display of an auxiliaryinput from a remote source. The input control signal auxiliary ready tosend AUX. RTS via path 638 is connected to the input of a conventionallevel changer 640 which changes EIA voltage compatible levels to TTLvoltage compatible levels. The output of the level changer 640 isconnected in parallel to one input of a two -input NOR gate 642 and to aflip-flop 644. The other input to NOR gate 642 is connected to the tapecontrol signal output TAPE of function decoder 544 provided via path564. The output of NOR gate 642 is also connected to flipflop 644 whichprovides the control signal enable line ELINE via path 462 in one stateand the control signal enable line ELINE via path 454 in the otherstate. The enable line output ELINE of flip-flop 644 provided via path454 is also connected in parallel to the input of a NOR gate 646 whoseoutput is connected to the input of another conventional level changer648 which changes TTL voltage compatible oevels to EIA voltagecompatible signal levels and provides as an output the control signalauxiliary clear to send AUX. CTS via path 650.

TEXT MEMORY PORTION Referring now to FIG. 5 and describing in greaterdetail the text memory portion 14 associated with the text input buffer12. As was previously mentioned, the text memory portion 14 preferablyincludes memories 52 and 54 which are preferably each recirculatingmemories. Both memory 52 and 54 each preferably comprise seven stages,one for each input bit, each stage preferably being 256 bits. Each ofthese memories 52 and 54 is a conventional recirculating memory networkand is represented by the symbol labeled MEMORY (7x256) which is asymbol defined as meaning seven stages, 256 bits each. The paralleloutput bits from storage register 46 (FIG. 4) are each connected inparallel to' the parallel inputs to memory 52 and memory 54,respectively, one bit per stage of each memory 52 and 54. In addition,as was previously mentioned, the load input terminal of memory 52 isconnected to the output of NOR gate 502 of address decoder 472 FIG. 4)via path 518 and the clear input terminal of memory 52 is connected tothe output of OR gate 520 of address decoder 472 (FIG. 4) via path 522.Similarly, as was also previously mentioned, the load input terminal ofmemory 54 is connected to the output of NOR gate 524 of address decoders472 (FIG. 4) via path 532 and the clear input terminal of memory 54 isconnected to the output of OR gate 530 of address decoder 472 (FIG. 4)via path 534. The parallel output bits of memory 52 are labeledrespectively MBlA, MB2A, MB3A, MB4A, MESA, MB6A and MB7A and areprovided via paths 660, 662, 664, 666, 668, 670 and 672, respectively,from memory 52. Similarly, the parallel output bits of memory 54 arelabeled, respectively, MBlB, MB2B, MB3B, MB4B, M1358, M1368 and MB7B andare provided via paths 674, 676, 678, 680, 682, 684 and 686,respectively, from memory 54.

As was previously mentioned, memories 52 and 54 havetheir outputsconnected in parallel to the recirculation register network 56 whichpreferably comprises seven recirculation registers 688, 690, 692, 694,696, 698 and 700, one register being provided for each bit, as will beexplained in greater detail hereinafter. Recirculation registers 688through 700 inclusive are preferably identical in structure andoperation, and are preferably conventional. For purposes of explanation,a typical recirculation register 688 is shown in greater detail in FIG.5. Each recirculation register 688 to 700 inclusive preferably includesa 32 bit register 702. Register 702 preferably has its clock inputconnected to a conventional clock generator shown in FIG. 7 via path 704so as to receive the clock signal CKR via path 704. A breakrecirculation control signal ikTz from coincidence circuit 514 of FIG. 7is connected in parallel to one input of a two input NAND gate 706 andtothe corresponding inputs of recirculation registers 690 through 700inclusive, via path 708. The other input to NAND gate 706 is therecirculation output of register 702.

Recirculation registers 688 through 700 inclusive are also provided withenable load signals E1 and E2,respectively, provided from a conventionalclock generator 710 of FIG. 7 via paths 712 and 714, respectively. Theenable load signal E1 is connected in parallel to one input of a NANDgate 716 and to the corresponding inputs of recirculation registers 690through 700 inclusive. The enable load signal E2 provided via path 714is connected in parallel to one input of another NAND gate 718 and tothe corresponding inputs of recirculation registers 690 through 700inclusive. The other input to NAND gate 716 is the parallel output bitfrom memory 52 provided via path 660 and the other input bit to NANDgate 718 is the parallel output bit of memory 54 provided via path 674.The outputs of NAND gate 706, 716 and 718 are connected in parallel. Theoutput of NAND gate 718 is also connected to the input of an inverter720 whose output is connected to the input of register 702.

The output of NAND gate 716 is the recirculation register output bit RBIprovided via path 722 to the character generator network 58 of displayportion 16, shown in greater detail in FIG. 6. Similarly, the paralleloutput bits from memories 52 and 54 provided via path 662 and 676,respectively are connected to the input of recirculation register 690whose output is recirculation bit R132 provided via path 724 to thecharacter generator network 58 of the display portion 16; the paralleloutputs of memories 52 and 54 provided via paths 664 and 678,respectively, are connected to the input of recirculation register 692whose output is recirculation bit RB3 provided via path 726 to thecharacter generator network 48 of display portion 16; the paralleloutput bits of memories 52 and 54 provided via paths 666 i and 680 areconnected to the input of recirculation register 694 whose output isrecirculation bit RB4 provided via path 728 to the character generatornetwork 58 of display portion 16; the parallel output bits of memories52 and 54 provided via paths 668 and 682 are connected to the inputs ofrecirculation register 696 whose output is recirculation bit RBSprovided via path 730 to the character generator network 58 of thedisplay portion 16; the parallel output bits of memories 52 and 54provided via paths 670 and 684 are connected to the input ofrecirculation register 698 whose output is recirculation bit RB6provided via path 732 to the character generator network 58 of displayportion 16; and the parallel output bits of memories 52 and 54 providedvia paths 672 and 686 are connected to the input of recirculationregister 700 whose output is recirculation bit RB7 provided via path 734to the character generator network 58 of display portion 16.

DISPLAY PORTION Referring now to FIG. 6 and describing the displayportion 16 in greater detail. Character generator network 58 preferablyincludes a pair of conventional character generators 736 and 738. Theseconventional character generators are preferably MOS read only memorieswhich are preprogrammed for the desired character generation functions.Preferably, character generator 736 is preprogrammed to providealphanumeric characters and fraction characters in response to therecirculation bits and the horizontal line scanning signals, andcharacter generator 738 is preferably preprogrammed to provide graphcharacters in response to the recirculation bits and the horizontal linescanning signals. The appropriate line scanning signals for tn'ggeringcharacter generators 736 and 738 will be discussed in greater detailwith reference to FIG. 7. The output of character generator 736, whichis preferably a plurality of parallel output bits, is connected to theinput of output register 60, which is preferably a conventional twostage output register. The clock input of the output register 60 isconnected via path 340 to the master oscillator associated with thebasic timing chain of FIG. 7. The transfer terminal input of outputregister 60 is connected to the transfer pulse output XFERTK of theoutput transfer portion 61 via path 63, output transfer portion 61preferably being similar in structure and operation to output transferportion 344 (FIG. 3).

The output of output register 60 is connected to one input of a twoinput OR gate 740. The other input to OR gate 740 is connected to theoutput of character generator 738. The output of OR gate 740 isconnected in parallel to one input of a pair of two input AND gates 62and 64, respectively. The other inputs of AND gates 62 and 64,respectively, are connected to the output of a conventional timinggenerator 746 labeled ENABLE TEXT GENERATOR (1 AND 2) which generator746 provides the timing pulse enable text 1 (ETXI) via path 748 to ANDgate 62, and the'timing pulse enable text 2 (ETX2) via path 750 to ANDgate 64. The timing signals utilized to control the operation of enabletext generator 746 are provided from the basic timing chain of FIG. 7and are, respectively, the timing signal output of the master oscillatorOSC provided via path 340, the VB3 timing signal output of the basictiming chain provided via path 446 and the R 2 timing signal outputprovided via path 752.

The output of AND gate 62, which is the information signal text data 1(TXDATAl is connected in parallel to the input of the three input ORgate 68. Another input to OR gate 68 is the scroll data output SCROLlprovided from the scroll character generation portion 26. The thirdinput to OR gate 68 is connected in parallel to the ticker data output'IKl of the ticker character generation portion 20 and to the output ofa two input AND gate 70. One input of AND gate 70 is the enable textsignal ETXZ provided via path 748. The other input to AND gate 70 isconnected in parallel to one input of another two input AND gate 84 andto the output of an inverter 764 whose input is connected to the TICKERoutput of position gating circuit 114 provided via path 432. The outputof AND gate 84 is connected in parallel to the ticker data input TK2associated with the ticker number 2 input buffer portion 22 to one Aswas previously mentioned, the output of OR gate 68 is connected to theinput of a conventional video mixer 74 together with the composite syncsignal output of the conventional mixed horizontal and vertical syncpulse generator 766 of FIG. 7 labeled SYNCI (represented by syncgenerator 76 in FIG. 1), provided via path 768. The'output of mixer 74,which is associated with channel A is a composite video signal output totelevision display device 78 which output is preferably a video displaysimilar to that illustrated in FIG. 8D, and which will be described ingreater detail in the discussion of the operation of the circuit.Similarly, the output of OR gate 80 is connected to the input of anotherconventional video mixer 86 together with the sync signal output SYNCZ(represented by sync generator 88 in FIG. 1) fromsync generator 766 ofFIG. 7 provided via path 770. The output of mixer 86, which isassociated with channel B is a composite video signal to TV displaydevice 90, similarly resulting in a video display preferably similar tothat illustrated in FIG. 8D. As will be discussed in the operation ofthe circuit, the video displays provided from mixers 74 and 86 need notbe the same and are preferably different.

TIMING SIGNAL GENERATION PORTION Referring now to FIG. 7 and describingin greater detail the timing signal generation portion which is thesource of the timing signals which control the operation of the variousportion of the system 10 and which has previously been referred to inthe detailed discussion of the other portions of system 10. The timinggenerator network shown in FIG. 7 includes the basic timing chainnetwork 772 which provides the horizontal line scanning timing signalsand the character counter timing signals utilized for controlling thetiming of the various portions of the system 10 in a manner to bediscussed in greater detail in the discussion of the operation of thesystem 10.

The basic timing chain 772 includes a master oscillator 774 of apredetermined frequency, such as 4.5 megahertz, which provides theoscillator clock signal OSC via path 340 and which is connected inparallel to the clock input of the video bit counter 776, which is I aconventional divide-by-six counter whose outputs are the timing signalsVBl, VB2 and VB3 provided on paths 448, 778 and 446, respectively.Preferably, counter 776 is a two stage counter consisting of adivide-by-two stage between output bits provided via paths 448 and 778,and a divide-by-three stage between output bits provided via paths 778and 446 so that timing signal VBl is equivalent to OSC/2, and VB2 andVB3 are each equivalent to OSC/6. The output of video bit counter 776 isconnected to the clock inputof a character counter 780 which ispreferably a conventional divide-by-48 counter which provides the timingsignal outputs C1, C2, C3, C4, C5 and C6 along paths 264, 270, 782,466,784 and 178, respectively. Preferably, these timing signals are suchthat Cl is equivalent to VB3/2, C2 is equivalent to VB3/4, C3 isequivalent to VB3/8, C4 is equivalent to VB3/l6, and C5 and C6 are eachequivalent to VB3/48. The output of character counter 780 is connectedto the clock input of a line counter 786 which is preferably aconventional divideby-eight counter whose outputs are L2", L2 and L2provided from counter 786 via paths 788, 790 and 792, respectively.Preferably, the timing signals L2", L2 and L2 are such that L2 isequivalent to C6/2, L2 is equivalent to C6/4 and L2 'is equivalent toC6/8. The output of line counter 786 is connected to the clock input ofa halfrow counter 794 which is preferably a conventional divide-by-twoflip-flop whose output is the timingsignal R/2 provided via path 796.Preferably, the timing signal R12 is equivalent to L2 /2.The output ofhalf-row counter 794 is connected to the clock input of a row counter798 which is preferably a conventional divide-byl 6 counter 798 whoseoutputs are R2, R2, R2 and R2 provided via paths 590, 800, 802 and 752,respectively.

The reset terminal of row counter 798 is connected to a line addernetwork 804 which provides a reset pulse RRC to row counter 798 at theend of six additional horizontal scan lines provided by line adder 804,as will be explained in greater detail hereinafter. Line adder 804includes flip-flops 806, 808 and 810. The R2 output of row counter 798provided via path 802 is connected to flip-flop 806. Flip-flop 806provides the timing signal R2 in the Q state and R2 in the 6 state. The6 output of'flip-flop 806 is connected in parallel to the data terminalinput of flip-flop 806 and to flip flop 808. The 0 state output offlip-flop 808 provides a signal which adds six horizontal scan lineslabeled m provided via path 812. In the 6 state, flip-flop 808 alsoprovides a signal which adds six horizontal scan lines labeled +6Lprovided via path 814. The 6 state output of flip-flop 808 is connectedin parallel to the

1. A system for providing character patterns for display on a displaydevice screen that utilizes a television raster scan-line pattern toprovide a composite video display, each character pattern beingdisplayed in one character space, said system comprising means forgenerating a first video display format of character patterns inresponse to a first digital signal; means for generating a second videodisplay format of character patterns in response to a second digitalsignal, said second format being different from said first format, saidfirst and second generated video display formats being independent fromeach other; and means for combining said first and second video displayformats to provide said composite video display for said display devicein which said first and second display formats occupy differentscan-line areas of said scan-line pattern on said screen; said characterspaces associated with said character patterns each being defined by apredetermined number of scan lines in said scan-line pattern and apredetermined number of elemental dots; said scan lines having a givendirection of scan with respect to said screen; said first video displayformat generating means including means for generating a plurality ofdot signals in repetitive sequences during said scan lines to correspondto elemental dots on said display device to divide said device in saidfirst video display format area in a first direction into a plurality ofsaid character spaces, and means for generating a plurality of linesignals in repetitive sequences in synchronism with said scan lines todivide said device in said first video display format area in a seconddirection into at least one row, the combination of a plurality of saiddot signals and a plurality of sequences of said line signals defining acharacter space; said first digital signal having an associatedinformation input rate to said first generating means, said first videodisplay format generating means further including means for controllablyperiodically shifting each of said character spaces in said row anincremental distance in a given direction parallel to said direction ofscan across said screen at a rate dependent on said information inputrate to controllably move the character patterns displayed in saidcharacter spaces in said given direction across said screen inaccordance with said input rate; said shifting means comprising meansfor varying said shifting rate in accordance with variations in saidinformation input rate for accelerating said character movement inaccordance with an acceleration in said information input rate and fordecelerating said character movement in accordance with a decelerationin said information input rate; said first video display formatgenerating means further comprising recirculating register storage meansfor receiving said first digital signal and loading therein saidcharacters in response thereto at an associated data loading ratecorresponding to said input rate, said storage register means having acharacter storage capacity of a plurality of said characters in length,and memory means operatively connected to said storage register meansfor receiving said characters therefrom upon transfer therefrom, saidshifting means comprising motion control means for providing a transfersignal to said storage register for incrementally transferring saidcharacters therefrom to said memory, said first video display formatbeing provided in response to an output from said memory, said motioncontrol means comprising means responsive to changes in said dataloading rate from providing a different motion control signal inresponse to a different quantity of characters being loaded into saidstorage register for a given character prior to said transfer, andposition gating means responsive To said motion control signals forcontrolling a change in incremental dot position of said given characterin said display in accordance with said change in said data loading ratewhereby the relative movement of said character patterns across saidscreen in said direction parallel to said direction of scan may becontrolled in accordance with said information input rate.
 2. A systemin accordance with claim 1 wherein each of said video display formats isindependently controllable.
 3. A system in accordance with claim 1wherein said line signal generating means generates said plurality ofline signals in repetitive sequences in synchronism with said scan linesto divide said device in said first video display format area in asecond direction into a plurality of rows, the combination of aplurality of said dot signals and a plurality of sequences of said linesignals defining a character space in a given one of said rows, thecharacter spaces in each of said rows being equal.
 4. A system inaccordance with claim 3 wherein said first video display formatgenerating means includes means for providing a complete characterpattern in at least a portion of said character space which is less thansaid total plurality of line signals.
 5. A system in accordance withclaim 4 wherein said first video display format generating meansincludes means for generating at least complete graph characterpatterns, a complete graph character pattern being provided in at leastsaid character space portion.
 6. A system in accordance with claim 4wherein said first video display format generating means includes meansfor generating at least complete graph character patterns andalphanumeric character patterns, a complete graph character patternbeing provided in at least said character space portion, and means forcontrolling which particular character pattern is to be displayed in agiven character space for each of said character spaces.
 7. A system inaccordance with claim 6 wherein said character pattern generating meansincludes means for generating fraction character patterns, said fractioncharacter patterns including a complete numerator character pattern anda complete denominator character pattern, said complete numeratorcharacter pattern being provided in a portion of a given character spacewhich is less than said total plurality of lines and dots, said completedenominator character pattern being provided in a different dot portionof said character space which is adjacent to said numerator characterspace dot portion, said denominator character pattern space line portionbeing lower than said numerator character pattern space line portion insaid first video display format, whereby a complete fraction characterpattern is provided in said adjacent character space portions.
 8. Asystem in accordance with claim 1 wherein said first video displayformat generating means includes means for providing a completecharacter pattern in a portion of said character space which is lessthan said total plurality of line signals.
 9. A system in accordancewith claim 8 wherein said first video display format generating meansincludes means for generating at least alphabetic character patterns, acomplete alphabetic character pattern being provided in said characterspace portion.
 10. A system in accordance with claim 8 wherein saidfirst video display format generating means includes means forgenerating at least alphanumeric character patterns, a completealphanumeric character pattern being provided in said character spaceportion.
 11. A system in accordance with claim 10 wherein each of saidcharacter spaces has an upper portion comprising a portion of said totalplurality of line signals and a lower portion comprising the balance ofsaid total plurality of line signals, said first video display formatgenerating means providing a ticker video display format wherein saidupper portions are utilized for providing complete alphabetic characterpatterns relating to a given stock ticker symbol and said lower portionsare utilized for providing at least complete numeric character patternsrelating to a given price associated with said symbol, only said upperportion or said lower portion of a given ticker video display formatcharacter space being utilized dependent on the type of stock tickerinformation to be displayed in a given character space.
 12. A system inaccordance with claim 8 wherein said first video display formatgenerating means includes means for generating at least fractioncharacter patterns, said fraction character patterns including acomplete numerator character pattern and a complete denominatorcharacter pattern, said complete numerator character pattern beingprovided in a portion of a given character space which is less than saidtotal plurality of lines and dots, said complete denominator characterpattern being provided in a different dot portion of said characterspace which is adjacent to said numerator character space dot portion,said denominator character pattern space line portion being lower thansaid numerator character pattern space line portion in said first videodisplay format, whereby a complete fraction character pattern isprovided in said adjacent character space portions.
 13. A system inaccordance with claim 8 wherein said first video display formatgenerating means includes means for generating at least completealphanumeric character patterns for said character space portions andfraction character patterns, said fraction character patterns includinga complete numerator character pattern and a complete denominatorcharacter pattern, said complete numerator character pattern beingprovided in a portion of a given character space which is less than saidtotal plurality of lines and dots, said complete denominator characterpattern being provided in a different dot portion of said characterspace which is adjacent to said numerator character space dot portion,said denominator character pattern space line portion being lower thansaid numerator character pattern space line portion in said first videodisplay format, whereby a complete fraction character pattern isprovided in said adjacent character space portions, said character spacecomprising 16 of said scan lines, said first video display formatgenerating means generating an alphabetic character pattern in acharacter space portion comprising the uppermost eight scan lines ofsaid 16 and a numeric character in a character space portion comprisingthe lowermost eight scan lines of said
 16. 14. A system in accordancewith claim 13 wherein said first video display format generating meansgenerates a denominator fraction character pattern in a character spaceportion comprising the lowermost five scan lines of said 16 and anumerator fraction character pattern in said character space portioncomprising the five scan lines of said 16 immediately above saidlowermost five scan lines.
 15. A system in accordance with claim 14wherein said numerator character space dot portion and said denominatorcharacter space dot portion each comprise at least half the totalplurality of dots.
 16. A system in accordance with claim 1 wherein saidsystem further includes means for controlling which character pattern isto be displayed in a given character space for each character space ofsaid first and second video display formats.
 17. A system in accordancewith claim 1 wherein said movement controlling means includes means forcontrolling the total number of character spaces across said screen insaid parallel direction in which said character patterns can bedisplayed.
 18. A system in accordance with claim 1 wherein said systemincludes means for inhibiting the generation of said second videodisplay format without affecting the generation of said first videodisplay format, said combining means including means for enabling onlysaid first video display format for said display device when said secOndvideo display format is inhibited.
 19. A system in accordance with claim1 wherein said motion control signal providing means comprises meanshaving a different associated motion control signal corresponding to anincrementally different quantity of said characters, said motion controlsignal being initially provided in accordance with said initial loadingrate and changing to incrementally increase said dot position change toa final initial value in accordance with an incremental increase in saidinitial loading rate as said character movement accelerate.
 20. A systemin accordance with claim 19 wherein said motion control signal providingmeans further comprises means for maintaining said motion control signalfinal initial value until the quantity of characters stored in saidstorage register decreases to a predetermined lower level, said motioncontrol signal changing to a control signal indicative of said lowerlevel quantity to decelerate said character movement.
 21. A system forproviding character patterns for display on a display device screen thatutilizes a television raster scan-line pattern to provide a compositevideo display, each character pattern being displayed in one characterspace, said system comprising means for generating at least a firstvideo display format of character patterns in response to a firstdigital signal; and means for providing said composite video display forsaid display device from said first video display format in which saidfirst display format occupies a given scan-line area of said scan-linepattern on said screen; said character spaces associated with saidcharacter patterns each being defined by a predetermined number of scanlines in said scan-line pattern and a predetermined number of elementaldots; said scan lines having a given direction of scan with respect tosaid screen; said first video display format generating means includingmeans for generating a plurality of dot signals in repetitive sequencesduring said scan lines to correspond to elemental dots on said displaydevice to divide said device to said first video display format area ina first direction into a plurality of said character spaces, and meansfor generating a plurality of line signals in repetitive sequences insynchronism with said scan lines to divide said device in said firstvideo display format area in a second direction into at least one row,the combination of a plurality of said dot signals and a plurality ofsequences of said line signals defining a character space; said firstdigital signal having an associated information input rate to said firstgenerating means, said first video display format generating meansfurther including means for controllably periodically shifting each ofsaid character spaces in said row an incremental distance in a givendirection parallel to said direction of scan across said screen at arate dependent on said information input rate to controllably move thecharacter patterns displayed in said character spaces in said givendirection across said screen in accordance with said input rate; saidshifting means comprising means for varying said shifting rate inaccordance with variations in said information input rate foraccelerating said character movement in accordance with an accelerationin said information input rate and for decelerating said charactermovement in accordance with a deceleration in said information inputrate; said first video display format generating means furthercomprising recirculating register storage means for receiving said firstdigital signal and loading therein said characters in response theretoat an associated data loading rate corresponding to said input rate,said storage register means having a character storage capacity of aplurality of said characters in length, and memory means operativelyconnected to said storage register means for receiving said characterstherefrom upon transfer therefrom, said shifting means comprising motioncontrol means for providing a transfer signal to said storage registerfor incrementally transferring said characters therefrom to said memory,said first video display format being provided in response to an outputfrom said memory, said motion control means comprising means responsiveto changes in said data loading rate for providing a different motioncontrol signal in response to a different quantity of characters beingloaded into said storage register for a given character prior to saidtransfer, and position gating means responsive to said motion controlsignals for controlling a change in incremental dot position of saidgiven character in said display in accordance with said change in saiddata loading rate whereby the relative movement of said characterpatterns across said screen in said direction parallel to said directionof scan may be controlled in accordance with said information inputrate.